The present invention relates to a nonvolatile memory device and method of fabricating the same.
In general, a memory cell of a nonvolatile memory device in which data is stored has a stacked gate structure. This stacked gate structure is formed by sequentially stacking a tunnel dielectric layer, a floating gate, an inter-gate dielectric layer, a control gate and a gate electrode layer over a channel region of the memory cell. The floating gate is used as a charge trap layer and is generally formed of a conductive layer such as polysilicon.
Meanwhile, a nonvolatile memory device using a non-conductive layer (for example, a nitride layer) as the charge trap layer instead of polysilicon has been proposed. The nonvolatile memory device using the non-conductive layer as the charge trap layer, as described above, can be classified into a SONOS (Silicon/Oxide/Nitride/Oxide/Silicon) nonvolatile memory device, a MANOS (Metal/Al2O3/Nitride/Oxide/Silicon) nonvolatile memory device, and so on depending on the material of a gate electrode layer, etc. This nonvolatile memory device has a tunnel dielectric layer forming a direct tunneling layer, a nitride layer for storing charges, an insulating layer used as a blocking layer, and a control gate electrode.
In the nonvolatile memory device using a conductive layer, such as polysilicon, as the charge trap layer, there is a problem that a retention time reduces significantly if any micro defect exists in the floating gate. However, in the nonvolatile memory device using a non-conductive layer, such as a nitride layer, as the charge trap layer, there is an advantage in that sensitivity to defects in process is relatively small due to the characteristic of the nitride layer.
Further, in the nonvolatile memory device using the conductive layer as the charge trap layer, there are limitations to the implementation of a low-voltage operation and a high-speed operation because the tunnel dielectric layer of about 70 angstroms or more in thickness is formed under the floating gate. However, in the nonvolatile memory device using the non-conductive layer as the charge trap layer, a memory device having a high-speed operation while requiring low voltage and low power can be implemented because a relatively thin direct tunneling dielectric layer is formed under the nitride layer.
In fabricating nonvolatile memory devices using the non-conductive layer as the charge trap layer, in general, isolation layers are formed in a semiconductor substrate through a STI (Shallow Trench Isolation) scheme, and a gate oxide layer, a nitride layer for storing charges, an oxide layer used as a blocking layer, a gate electrode layer, and so on are formed over the semiconductor substrate including the isolation layers. A gate pattern process is then performed to thereby form a gate constituting a memory cell.
However, if a flash memory device using this non-conductive layer as the charge trap layer is fabricated, the nitride layers for storing charges are not formed in respective memory cells separately, but are interconnected in the direction of the memory cells even after the gate pattern process is carried out. In this case, charges trapped in the charge trap layer included in a specific memory cell can diffuse into neighboring memory cells in a horizontal direction as time goes by.
FIG. 1 is a sectional view illustrating a conventional method of fabricating a MANOS type nonvolatile memory device.
Referring to FIG. 1, a semiconductor substrate 10 is etched to thereby form trenches. The trenches are gap-filled with an insulating layer, forming isolation layers 11. A tunnel dielectric layer 12 is then formed over an active region of the semiconductor device. A charge trap layer 13, a blocking insulating layer 14, a metal electrode layer 15, and gate electrode layers 16, 17 are sequentially formed over the entire surface. A gate pattern etch process is then performed to thereby form a gate of a cell region.
In the conventional MANOS type nonvolatile memory device, the charge trap layer 13 is also formed on an isolation region between active regions. Thus, if baking is performed at high temperature after programming is carried out by trapping charges in the charge trap layer 13, the trapped charges move to neighboring gates, which may lower a program threshold voltage. It leads to a degraded retention characteristic (i.e., the charge retention capability of a cell).
FIG. 2 is a sectional view illustrating a conventional method of fabricating a SONOS type nonvolatile memory device.
Referring to FIG. 2, an isolation region of a semiconductor substrate 20 is etched to thereby form isolation trenches. The trenches are gap-filled with an insulating layer, forming isolation layers 21. A tunnel dielectric layer 22, a charge trap layer 23, a blocking layer 24, a conductive layer 25 for a control gate, and a gate electrode layer 26 are sequentially stacked over the entire surface including the isolation layers 21.
In the conventional SONOS type nonvolatile memory device, a low voltage transistor and a high voltage transistor are first formed in a peri region (i.e., a peripheral region), and a cell to be used as a storage medium is then formed. In accordance with the above method, the charge trap layer of the cell region is shared with neighboring cells in the word line direction. Due to this, a problem may arise because trapped charges may move to neighboring gates, thereby lowering the program threshold voltage of a cell. It leads to a degraded retention characteristic (i.e., the charge retention capability of a cell).
Further, the charge trapping efficiency of the charge trap layer is about 70% compared with that of the floating gate because not all the charges passing through the tunnel dielectric layer are trapped, but only part of them are trapped. In this case, the threshold voltage corresponding to such short efficiency must be compensated for by increasing a program bias, but it is very difficult to form a high voltage transistor for transferring a high voltage.